Support more SIMD intrinsics and refactor argument adjustment
This commit is contained in:
Antoni Boucher
parent
eba654c57a
commit
4b40ac790d
2 changed files with 194 additions and 126 deletions
113
src/builder.rs
113
src/builder.rs
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@ -48,6 +48,7 @@ use rustc_target::spec::{HasTargetSpec, Target};
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use crate::common::{SignType, TypeReflection, type_is_pointer};
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use crate::context::CodegenCx;
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use crate::intrinsic::llvm;
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use crate::type_of::LayoutGccExt;
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// TODO(antoyo)
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@ -224,18 +225,8 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> {
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.zip(args.iter())
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.enumerate()
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.map(|(index, (expected_ty, &actual_val))| {
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// NOTE: these intrinsics have missing parameters before the last one, so ignore the
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// last argument type check.
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// FIXME(antoyo): find a way to refactor in order to avoid this hack.
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match &*func_name {
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"__builtin_ia32_maxps512_mask" | "__builtin_ia32_maxpd512_mask"
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| "__builtin_ia32_minps512_mask" | "__builtin_ia32_minpd512_mask" | "__builtin_ia32_sqrtps512_mask"
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| "__builtin_ia32_sqrtpd512_mask" => {
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if index == args.len() - 1 {
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return actual_val;
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}
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},
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_ => (),
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if llvm::ignore_arg_cast(&func_name, index, args.len()) {
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return actual_val;
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}
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let actual_ty = actual_val.get_type();
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@ -302,7 +293,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> {
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}
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fn function_ptr_call(&mut self, func_ptr: RValue<'gcc>, args: &[RValue<'gcc>], _funclet: Option<&Funclet>) -> RValue<'gcc> {
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let mut args = self.check_ptr_call("call", func_ptr, args);
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let args = self.check_ptr_call("call", func_ptr, args);
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// gccjit requires to use the result of functions, even when it's not used.
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// That's why we assign the result to a local or call add_eval().
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@ -314,92 +305,8 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> {
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if return_type != void_type {
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unsafe { RETURN_VALUE_COUNT += 1 };
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let result = current_func.new_local(None, return_type, &format!("ptrReturnValue{}", unsafe { RETURN_VALUE_COUNT }));
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// Some LLVM intrinsics do not map 1-to-1 to GCC intrinsics, so we add the missing
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// arguments here.
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if gcc_func.get_param_count() != args.len() {
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let func_name = format!("{:?}", func_ptr);
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match &*func_name {
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"__builtin_ia32_pmuldq512_mask" | "__builtin_ia32_pmuludq512_mask"
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// FIXME(antoyo): the following intrinsics has 4 (or 5) arguments according to the doc, but is defined with 2 (or 3) arguments in library/stdarch/crates/core_arch/src/x86/avx512f.rs.
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| "__builtin_ia32_pmaxsd512_mask" | "__builtin_ia32_pmaxsq512_mask" | "__builtin_ia32_pmaxsq256_mask"
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| "__builtin_ia32_pmaxsq128_mask" | "__builtin_ia32_maxps512_mask" | "__builtin_ia32_maxpd512_mask"
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| "__builtin_ia32_pmaxud512_mask" | "__builtin_ia32_pmaxuq512_mask" | "__builtin_ia32_pmaxuq256_mask"
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| "__builtin_ia32_pmaxuq128_mask"
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| "__builtin_ia32_pminsd512_mask" | "__builtin_ia32_pminsq512_mask" | "__builtin_ia32_pminsq256_mask"
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| "__builtin_ia32_pminsq128_mask" | "__builtin_ia32_minps512_mask" | "__builtin_ia32_minpd512_mask"
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| "__builtin_ia32_pminud512_mask" | "__builtin_ia32_pminuq512_mask" | "__builtin_ia32_pminuq256_mask"
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| "__builtin_ia32_pminuq128_mask" | "__builtin_ia32_sqrtps512_mask" | "__builtin_ia32_sqrtpd512_mask"
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=> {
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// TODO: refactor by separating those intrinsics outside of this branch.
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let add_before_last_arg =
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match &*func_name {
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"__builtin_ia32_maxps512_mask" | "__builtin_ia32_maxpd512_mask"
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| "__builtin_ia32_minps512_mask" | "__builtin_ia32_minpd512_mask"
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| "__builtin_ia32_sqrtps512_mask" | "__builtin_ia32_sqrtpd512_mask" => true,
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_ => false,
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};
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let new_first_arg_is_zero =
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match &*func_name {
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"__builtin_ia32_pmaxuq256_mask" | "__builtin_ia32_pmaxuq128_mask"
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| "__builtin_ia32_pminuq256_mask" | "__builtin_ia32_pminuq128_mask" => true,
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_ => false
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};
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let arg3_index =
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match &*func_name {
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"__builtin_ia32_sqrtps512_mask" | "__builtin_ia32_sqrtpd512_mask" => 1,
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_ => 2,
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};
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let mut new_args = args.to_vec();
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let arg3_type = gcc_func.get_param_type(arg3_index);
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let first_arg =
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if new_first_arg_is_zero {
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let vector_type = arg3_type.dyncast_vector().expect("vector type");
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let zero = self.context.new_rvalue_zero(vector_type.get_element_type());
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let num_units = vector_type.get_num_units();
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self.context.new_rvalue_from_vector(None, arg3_type, &vec![zero; num_units])
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}
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else {
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self.current_func().new_local(None, arg3_type, "undefined_for_intrinsic").to_rvalue()
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};
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if add_before_last_arg {
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new_args.insert(new_args.len() - 1, first_arg);
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}
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else {
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new_args.push(first_arg);
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}
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let arg4_index =
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match &*func_name {
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"__builtin_ia32_sqrtps512_mask" | "__builtin_ia32_sqrtpd512_mask" => 2,
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_ => 3,
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};
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let arg4_type = gcc_func.get_param_type(arg4_index);
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let minus_one = self.context.new_rvalue_from_int(arg4_type, -1);
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if add_before_last_arg {
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new_args.insert(new_args.len() - 1, minus_one);
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}
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else {
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new_args.push(minus_one);
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}
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args = new_args.into();
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},
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"__builtin_ia32_vfmaddps512_mask" | "__builtin_ia32_vfmaddpd512_mask" => {
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let mut new_args = args.to_vec();
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if args.len() == 3 {
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// Both llvm.fma.v16f32 and llvm.x86.avx512.vfmaddsub.ps.512 maps to
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// the same GCC intrinsic, but the former has 3 parameters and the
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// latter has 4 so it doesn't require this additional argument.
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let arg4_type = gcc_func.get_param_type(3);
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let minus_one = self.context.new_rvalue_from_int(arg4_type, -1);
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new_args.push(minus_one);
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}
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let arg5_type = gcc_func.get_param_type(4);
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new_args.push(self.context.new_rvalue_from_int(arg5_type, 4));
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args = new_args.into();
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},
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_ => (),
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}
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}
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let func_name = format!("{:?}", func_ptr);
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let args = llvm::adjust_intrinsic_arguments(&self, gcc_func, args, &func_name);
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self.block.add_assignment(None, result, self.cx.context.new_call_through_ptr(None, func_ptr, &args));
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result.to_rvalue()
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}
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@ -1514,11 +1421,11 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> {
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self.vector_reduce(src, |a, b, context| context.new_binary_op(None, op, a.get_type(), a, b))
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}
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pub fn vector_reduce_fadd_fast(&mut self, acc: RValue<'gcc>, src: RValue<'gcc>) -> RValue<'gcc> {
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pub fn vector_reduce_fadd_fast(&mut self, _acc: RValue<'gcc>, _src: RValue<'gcc>) -> RValue<'gcc> {
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unimplemented!();
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}
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pub fn vector_reduce_fmul_fast(&mut self, acc: RValue<'gcc>, src: RValue<'gcc>) -> RValue<'gcc> {
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pub fn vector_reduce_fmul_fast(&mut self, _acc: RValue<'gcc>, _src: RValue<'gcc>) -> RValue<'gcc> {
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unimplemented!();
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}
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@ -1553,6 +1460,10 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> {
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let ones = vec![self.context.new_rvalue_one(element_type); num_units];
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let ones = self.context.new_rvalue_from_vector(None, cond_type, &ones);
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let inverted_masks = masks + ones;
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// NOTE: sometimes, the type of else_val can be different than the type of then_val in
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// libgccjit (vector of int vs vector of int32_t), but they should be the same for the AND
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// operation to work.
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let else_val = self.context.new_bitcast(None, else_val, then_val.get_type());
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let else_vals = inverted_masks & else_val;
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then_vals | else_vals
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@ -1,6 +1,169 @@
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use gccjit::Function;
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use std::borrow::Cow;
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use crate::context::CodegenCx;
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use gccjit::{Function, FunctionPtrType, RValue, ToRValue};
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use crate::{context::CodegenCx, builder::Builder};
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pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc, 'tcx>, gcc_func: FunctionPtrType<'gcc>, mut args: Cow<'b, [RValue<'gcc>]>, func_name: &str) -> Cow<'b, [RValue<'gcc>]> {
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// Some LLVM intrinsics do not map 1-to-1 to GCC intrinsics, so we add the missing
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// arguments here.
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if gcc_func.get_param_count() != args.len() {
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match &*func_name {
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"__builtin_ia32_pmuldq512_mask" | "__builtin_ia32_pmuludq512_mask"
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// FIXME(antoyo): the following intrinsics has 4 (or 5) arguments according to the doc, but is defined with 2 (or 3) arguments in library/stdarch/crates/core_arch/src/x86/avx512f.rs.
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| "__builtin_ia32_pmaxsd512_mask" | "__builtin_ia32_pmaxsq512_mask" | "__builtin_ia32_pmaxsq256_mask"
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| "__builtin_ia32_pmaxsq128_mask" | "__builtin_ia32_maxps512_mask" | "__builtin_ia32_maxpd512_mask"
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| "__builtin_ia32_pmaxud512_mask" | "__builtin_ia32_pmaxuq512_mask" | "__builtin_ia32_pmaxuq256_mask"
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| "__builtin_ia32_pmaxuq128_mask"
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| "__builtin_ia32_pminsd512_mask" | "__builtin_ia32_pminsq512_mask" | "__builtin_ia32_pminsq256_mask"
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| "__builtin_ia32_pminsq128_mask" | "__builtin_ia32_minps512_mask" | "__builtin_ia32_minpd512_mask"
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| "__builtin_ia32_pminud512_mask" | "__builtin_ia32_pminuq512_mask" | "__builtin_ia32_pminuq256_mask"
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| "__builtin_ia32_pminuq128_mask" | "__builtin_ia32_sqrtps512_mask" | "__builtin_ia32_sqrtpd512_mask"
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=> {
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// TODO: refactor by separating those intrinsics outside of this branch.
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let add_before_last_arg =
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match &*func_name {
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"__builtin_ia32_maxps512_mask" | "__builtin_ia32_maxpd512_mask"
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| "__builtin_ia32_minps512_mask" | "__builtin_ia32_minpd512_mask"
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| "__builtin_ia32_sqrtps512_mask" | "__builtin_ia32_sqrtpd512_mask" => true,
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_ => false,
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};
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let new_first_arg_is_zero =
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match &*func_name {
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"__builtin_ia32_pmaxuq256_mask" | "__builtin_ia32_pmaxuq128_mask"
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| "__builtin_ia32_pminuq256_mask" | "__builtin_ia32_pminuq128_mask" => true,
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_ => false
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};
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let arg3_index =
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match &*func_name {
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"__builtin_ia32_sqrtps512_mask" | "__builtin_ia32_sqrtpd512_mask" => 1,
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_ => 2,
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};
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let mut new_args = args.to_vec();
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let arg3_type = gcc_func.get_param_type(arg3_index);
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let first_arg =
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if new_first_arg_is_zero {
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let vector_type = arg3_type.dyncast_vector().expect("vector type");
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let zero = builder.context.new_rvalue_zero(vector_type.get_element_type());
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let num_units = vector_type.get_num_units();
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builder.context.new_rvalue_from_vector(None, arg3_type, &vec![zero; num_units])
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}
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else {
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builder.current_func().new_local(None, arg3_type, "undefined_for_intrinsic").to_rvalue()
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};
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if add_before_last_arg {
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new_args.insert(new_args.len() - 1, first_arg);
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}
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else {
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new_args.push(first_arg);
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}
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let arg4_index =
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match &*func_name {
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"__builtin_ia32_sqrtps512_mask" | "__builtin_ia32_sqrtpd512_mask" => 2,
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_ => 3,
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};
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let arg4_type = gcc_func.get_param_type(arg4_index);
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let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1);
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if add_before_last_arg {
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new_args.insert(new_args.len() - 1, minus_one);
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}
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else {
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new_args.push(minus_one);
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}
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args = new_args.into();
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},
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"__builtin_ia32_pternlogd512_mask" | "__builtin_ia32_pternlogd256_mask"
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| "__builtin_ia32_pternlogd128_mask" | "__builtin_ia32_pternlogq512_mask"
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| "__builtin_ia32_pternlogq256_mask" | "__builtin_ia32_pternlogq128_mask" => {
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let mut new_args = args.to_vec();
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let arg5_type = gcc_func.get_param_type(4);
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let minus_one = builder.context.new_rvalue_from_int(arg5_type, -1);
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new_args.push(minus_one);
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args = new_args.into();
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},
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"__builtin_ia32_vfmaddps512_mask" | "__builtin_ia32_vfmaddpd512_mask" => {
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let mut new_args = args.to_vec();
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let mut last_arg = None;
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if args.len() == 4 {
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last_arg = new_args.pop();
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}
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let arg4_type = gcc_func.get_param_type(3);
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let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1);
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new_args.push(minus_one);
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if args.len() == 3 {
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// Both llvm.fma.v16f32 and llvm.x86.avx512.vfmadd.ps.512 maps to
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// the same GCC intrinsic, but the former has 3 parameters and the
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// latter has 4 so it doesn't require this additional argument.
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let arg5_type = gcc_func.get_param_type(4);
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new_args.push(builder.context.new_rvalue_from_int(arg5_type, 4));
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}
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if let Some(last_arg) = last_arg {
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new_args.push(last_arg);
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}
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args = new_args.into();
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},
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"__builtin_ia32_subps512_mask" | "__builtin_ia32_subpd512_mask"
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| "__builtin_ia32_mulps512_mask" | "__builtin_ia32_mulpd512_mask"
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| "__builtin_ia32_divps512_mask" | "__builtin_ia32_divpd512_mask"
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| "__builtin_ia32_vfmaddsubps512_mask" | "__builtin_ia32_vfmaddsubpd512_mask" => {
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let mut new_args = args.to_vec();
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let last_arg = new_args.pop().expect("last arg");
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let arg4_type = gcc_func.get_param_type(3);
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let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1);
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new_args.push(minus_one);
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new_args.push(last_arg);
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args = new_args.into();
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},
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"__builtin_ia32_addps512_mask" | "__builtin_ia32_addpd512_mask" => {
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let mut new_args = args.to_vec();
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let last_arg = new_args.pop().expect("last arg");
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let arg3_type = gcc_func.get_param_type(2);
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let undefined = builder.current_func().new_local(None, arg3_type, "undefined_for_intrinsic").to_rvalue();
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new_args.push(undefined);
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let arg4_type = gcc_func.get_param_type(3);
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let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1);
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new_args.push(minus_one);
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new_args.push(last_arg);
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args = new_args.into();
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},
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_ => (),
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}
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}
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args
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}
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pub fn ignore_arg_cast(func_name: &str, index: usize, args_len: usize) -> bool {
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// NOTE: these intrinsics have missing parameters before the last one, so ignore the
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// last argument type check.
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// FIXME(antoyo): find a way to refactor in order to avoid this hack.
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match func_name {
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"__builtin_ia32_maxps512_mask" | "__builtin_ia32_maxpd512_mask"
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| "__builtin_ia32_minps512_mask" | "__builtin_ia32_minpd512_mask" | "__builtin_ia32_sqrtps512_mask"
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| "__builtin_ia32_sqrtpd512_mask" | "__builtin_ia32_addps512_mask" | "__builtin_ia32_addpd512_mask"
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| "__builtin_ia32_subps512_mask" | "__builtin_ia32_subpd512_mask"
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| "__builtin_ia32_mulps512_mask" | "__builtin_ia32_mulpd512_mask"
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| "__builtin_ia32_divps512_mask" | "__builtin_ia32_divpd512_mask"
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| "__builtin_ia32_vfmaddsubps512_mask" | "__builtin_ia32_vfmaddsubpd512_mask" => {
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if index == args_len - 1 {
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return true;
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}
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},
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"__builtin_ia32_vfmaddps512_mask" => {
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if args_len == 4 && index == args_len - 1 {
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return true;
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}
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},
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_ => (),
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}
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false
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}
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#[cfg(not(feature="master"))]
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pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function<'gcc> {
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@ -37,29 +200,23 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function
|
|||
"llvm.x86.avx512.mask.pminu.q.128" => "__builtin_ia32_pminuq128_mask",
|
||||
"llvm.fma.v16f32" => "__builtin_ia32_vfmaddps512_mask",
|
||||
"llvm.fma.v8f64" => "__builtin_ia32_vfmaddpd512_mask",
|
||||
"llvm.x86.avx512.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddps512_mask",
|
||||
"llvm.x86.avx512.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddpd512_mask",
|
||||
"llvm.x86.avx512.rcp14.ps.256" => "__builtin_ia32_rcp14ps256_mask",
|
||||
"llvm.x86.avx512.rcp14.ps.128" => "__builtin_ia32_rcp14ps128_mask",
|
||||
"llvm.x86.avx512.rcp14.pd.256" => "__builtin_ia32_rcp14pd256_mask",
|
||||
"llvm.x86.avx512.rcp14.pd.128" => "__builtin_ia32_rcp14pd128_mask",
|
||||
"llvm.x86.avx512.rsqrt14.ps.256" => "__builtin_ia32_rsqrt14ps256_mask",
|
||||
"llvm.x86.avx512.rsqrt14.ps.128" => "__builtin_ia32_rsqrt14ps128_mask",
|
||||
"llvm.x86.avx512.rsqrt14.pd.256" => "__builtin_ia32_rsqrt14pd256_mask",
|
||||
"llvm.x86.avx512.rsqrt14.pd.128" => "__builtin_ia32_rsqrt14pd128_mask",
|
||||
"llvm.x86.avx512.mask.getexp.ps.512" => "__builtin_ia32_getexpps512_mask",
|
||||
"llvm.x86.avx512.mask.getexp.ps.256" => "__builtin_ia32_getexpps256_mask",
|
||||
"llvm.x86.avx512.mask.getexp.ps.128" => "__builtin_ia32_getexpps128_mask",
|
||||
"llvm.x86.avx512.mask.getexp.pd.512" => "__builtin_ia32_getexppd512_mask",
|
||||
"llvm.x86.avx512.mask.getexp.pd.256" => "__builtin_ia32_getexppd256_mask",
|
||||
"llvm.x86.avx512.mask.getexp.pd.128" => "__builtin_ia32_getexppd128_mask",
|
||||
"llvm.x86.avx512.mask.rndscale.ps.256" => "__builtin_ia32_rndscaleps_256_mask",
|
||||
"llvm.x86.avx512.mask.rndscale.ps.128" => "__builtin_ia32_rndscaleps_128_mask",
|
||||
"llvm.x86.avx512.mask.rndscale.pd.256" => "__builtin_ia32_rndscalepd_256_mask",
|
||||
"llvm.x86.avx512.mask.rndscale.pd.128" => "__builtin_ia32_rndscalepd_128_mask",
|
||||
"llvm.x86.avx512.mask.scalef.ps.512" => "__builtin_ia32_scalefps512_mask",
|
||||
"llvm.x86.avx512.mask.scalef.ps.256" => "__builtin_ia32_scalefps256_mask",
|
||||
"llvm.x86.avx512.mask.scalef.ps.128" => "__builtin_ia32_scalefps128_mask",
|
||||
"llvm.x86.avx512.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddsubps512_mask",
|
||||
"llvm.x86.avx512.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddsubpd512_mask",
|
||||
"llvm.x86.avx512.pternlog.d.512" => "__builtin_ia32_pternlogd512_mask",
|
||||
"llvm.x86.avx512.pternlog.d.256" => "__builtin_ia32_pternlogd256_mask",
|
||||
"llvm.x86.avx512.pternlog.d.128" => "__builtin_ia32_pternlogd128_mask",
|
||||
"llvm.x86.avx512.pternlog.q.512" => "__builtin_ia32_pternlogq512_mask",
|
||||
"llvm.x86.avx512.pternlog.q.256" => "__builtin_ia32_pternlogq256_mask",
|
||||
"llvm.x86.avx512.pternlog.q.128" => "__builtin_ia32_pternlogq128_mask",
|
||||
"llvm.x86.avx512.add.ps.512" => "__builtin_ia32_addps512_mask",
|
||||
"llvm.x86.avx512.add.pd.512" => "__builtin_ia32_addpd512_mask",
|
||||
"llvm.x86.avx512.sub.ps.512" => "__builtin_ia32_subps512_mask",
|
||||
"llvm.x86.avx512.sub.pd.512" => "__builtin_ia32_subpd512_mask",
|
||||
"llvm.x86.avx512.mul.ps.512" => "__builtin_ia32_mulps512_mask",
|
||||
"llvm.x86.avx512.mul.pd.512" => "__builtin_ia32_mulpd512_mask",
|
||||
"llvm.x86.avx512.div.ps.512" => "__builtin_ia32_divps512_mask",
|
||||
"llvm.x86.avx512.div.pd.512" => "__builtin_ia32_divpd512_mask",
|
||||
"llvm.x86.avx512.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_mask",
|
||||
|
||||
// The above doc points to unknown builtins for the following, so override them:
|
||||
"llvm.x86.avx2.gather.d.d" => "__builtin_ia32_gathersiv4si",
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue