Make vreg constrs per-quad, regfence on nontrivial constrs, back out workaround to _uint, add regression test. Closes #152.
This commit is contained in:
Graydon Hoare
parent
a7eeeb596a
commit
7cfa7bdd23
4 changed files with 73 additions and 49 deletions
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@ -510,6 +510,7 @@ TEST_XFAILS_LLVM := $(TASK_XFAILS) \
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obj-with-vec.rs \
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operator-associativity.rs \
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output-slot-variants.rs \
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over-constrained-vregs.rs \
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pred.rs \
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preempt.rs \
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readalias.rs \
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@ -322,38 +322,34 @@ let dump_quads cx =
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done
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;;
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let calculate_vreg_constraints (cx:ctxt) : Bits.t array =
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let calculate_vreg_constraints
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(cx:ctxt)
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(constraints:Bits.t array)
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(q:quad)
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: unit =
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let abi = cx.ctxt_abi in
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let n_vregs = cx.ctxt_n_vregs in
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let n_hregs = abi.Abi.abi_n_hardregs in
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let constraints = Array.init n_vregs (fun _ -> Bits.create n_hregs true) in
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Array.iteri
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Array.iter (fun c -> Bits.clear c; Bits.invert c) constraints;
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abi.Abi.abi_constrain_vregs q constraints;
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iflog cx
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begin
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fun i q ->
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abi.Abi.abi_constrain_vregs q constraints;
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iflog cx
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begin
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fun _ ->
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let hr_str = cx.ctxt_abi.Abi.abi_str_of_hardreg in
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log cx "constraints for quad %d = %s"
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i (string_of_quad hr_str q);
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let qp_reg _ r =
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begin
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match r with
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Il.Hreg _ -> ()
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| Il.Vreg v ->
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let hregs = Bits.to_list constraints.(v) in
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log cx "<v%d> constrained to hregs: [%s]"
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v (list_to_str hregs hr_str)
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end;
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r
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in
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ignore (Il.process_quad { Il.identity_processor with
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Il.qp_reg = qp_reg } q)
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end;
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fun _ ->
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let hr_str = cx.ctxt_abi.Abi.abi_str_of_hardreg in
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log cx "constraints for quad %s"
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(string_of_quad hr_str q);
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let qp_reg _ r =
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begin
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match r with
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Il.Hreg _ -> ()
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| Il.Vreg v ->
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let hregs = Bits.to_list constraints.(v) in
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log cx "<v%d> constrained to hregs: [%s]"
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v (list_to_str hregs hr_str)
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end;
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r
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in
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ignore (Il.process_quad { Il.identity_processor with
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Il.qp_reg = qp_reg } q)
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end
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cx.ctxt_quads;
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constraints
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;;
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(* Simple local register allocator. Nothing fancy. *)
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@ -380,8 +376,10 @@ let reg_alloc
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let (live_in_vregs, live_out_vregs) =
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calculate_live_bitvectors cx
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in
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let n_vregs = cx.ctxt_n_vregs in
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let n_hregs = abi.Abi.abi_n_hardregs in
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let (vreg_constraints:Bits.t array) = (* vreg idx -> hreg bits.t *)
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calculate_vreg_constraints cx
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Array.init n_vregs (fun _ -> Bits.create n_hregs true)
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in
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let inactive_hregs = ref [] in (* [hreg] *)
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let active_hregs = ref [] in (* [hreg] *)
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@ -560,23 +558,40 @@ let reg_alloc
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for i = 0 to (Array.length cx.ctxt_quads) - 1
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do
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let quad = cx.ctxt_quads.(i) in
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let _ = calculate_vreg_constraints cx vreg_constraints quad in
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let clobbers = cx.ctxt_abi.Abi.abi_clobbers quad in
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let used = quad_used_vregs quad in
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let defined = quad_defined_vregs quad in
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let vreg_constrs v = (v, Bits.to_list (vreg_constraints.(v))) in
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let used_constrs = List.map vreg_constrs used in
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let constrs_collide (v1,c1) =
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if List.length c1 <> 1
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then false
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else
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List.exists
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(fun (v2,c2) -> if v1 = v2 then false else c1 = c2)
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used_constrs
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in
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begin
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if List.exists constrs_collide used_constrs
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then raise (Ra_error ("over-constrained vregs"));
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(* If the quad has any nontrivial vreg constraints, regfence.
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* This is awful but it saves us from cached/constrained
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* interference as was found in issue #152. *)
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if List.exists
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(fun v -> not (Bits.equal vreg_constraints.(v) all_hregs))
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used
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then
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begin
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(* Regfence. *)
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spill_all_regs i;
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(* Check for over-constrained-ness after any such regfence. *)
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let vreg_constrs v =
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(v, Bits.to_list (vreg_constraints.(v)))
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in
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let constrs = List.map vreg_constrs (used @ defined) in
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let constrs_collide (v1,c1) =
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if List.length c1 <> 1
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then false
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else
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List.exists
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(fun (v2,c2) -> if v1 = v2 then false else c1 = c2)
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constrs
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in
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if List.exists constrs_collide constrs
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then raise (Ra_error ("over-constrained vregs"));
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end;
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if List.exists (fun def -> List.mem def clobbers) defined
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then raise (Ra_error ("clobber and defined sets overlap"));
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iflog cx
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@ -640,10 +655,10 @@ let reg_alloc
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end;
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(cx.ctxt_quads, cx.ctxt_next_spill)
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with
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Ra_error s ->
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Session.fail sess "RA error: %s\n" s;
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(quads, 0)
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with
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Ra_error s ->
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Session.fail sess "RA error: %s\n" s;
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(quads, 0)
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;;
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@ -28,9 +28,7 @@ fn next_power_of_two(uint n) -> uint {
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let uint shift = 1u;
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while (shift <= halfbits) {
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tmp |= tmp >> shift;
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// FIXME (issue #152): This would be just a tad cuter if it were
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// shift <<= 1u
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shift = shift << 1u;
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shift <<= 1u;
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}
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ret tmp + 1u;
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}
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10
src/test/run-pass/over-constrained-vregs.rs
Normal file
10
src/test/run-pass/over-constrained-vregs.rs
Normal file
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@ -0,0 +1,10 @@
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// Regression test for issue #152.
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fn main() {
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let uint b = 1u;
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while (b <= 32u) {
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0u << b;
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b <<= 1u;
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log b;
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}
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}
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