Merge pull request #1206 from nbdd0121/master
Improve inline asm support
This commit is contained in:
bjorn3
GitHub
commit
a49c6b8a57
1 changed files with 484 additions and 155 deletions
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@ -6,6 +6,7 @@ use std::fmt::Write;
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use rustc_ast::ast::{InlineAsmOptions, InlineAsmTemplatePiece};
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use rustc_middle::mir::InlineAsmOperand;
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use rustc_span::Symbol;
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use rustc_target::asm::*;
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pub(crate) fn codegen_inline_asm<'tcx>(
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@ -41,8 +42,10 @@ pub(crate) fn codegen_inline_asm<'tcx>(
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assert_eq!(operands.len(), 4);
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let (leaf, eax_place) = match operands[1] {
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InlineAsmOperand::InOut { reg, late: true, ref in_value, out_place } => {
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let reg = expect_reg(reg);
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assert_eq!(reg, InlineAsmReg::X86(X86InlineAsmReg::ax));
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assert_eq!(
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reg,
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InlineAsmRegOrRegClass::Reg(InlineAsmReg::X86(X86InlineAsmReg::ax))
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);
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(
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crate::base::codegen_operand(fx, in_value).load_scalar(fx),
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crate::base::codegen_place(fx, out_place.unwrap()),
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@ -64,8 +67,10 @@ pub(crate) fn codegen_inline_asm<'tcx>(
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};
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let (sub_leaf, ecx_place) = match operands[2] {
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InlineAsmOperand::InOut { reg, late: true, ref in_value, out_place } => {
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let reg = expect_reg(reg);
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assert_eq!(reg, InlineAsmReg::X86(X86InlineAsmReg::cx));
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assert_eq!(
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reg,
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InlineAsmRegOrRegClass::Reg(InlineAsmReg::X86(X86InlineAsmReg::cx))
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);
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(
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crate::base::codegen_operand(fx, in_value).load_scalar(fx),
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crate::base::codegen_place(fx, out_place.unwrap()),
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@ -75,8 +80,10 @@ pub(crate) fn codegen_inline_asm<'tcx>(
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};
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let edx_place = match operands[3] {
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InlineAsmOperand::Out { reg, late: true, place } => {
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let reg = expect_reg(reg);
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assert_eq!(reg, InlineAsmReg::X86(X86InlineAsmReg::dx));
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assert_eq!(
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reg,
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InlineAsmRegOrRegClass::Reg(InlineAsmReg::X86(X86InlineAsmReg::dx))
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);
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crate::base::codegen_place(fx, place.unwrap())
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}
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_ => unreachable!(),
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@ -96,60 +103,55 @@ pub(crate) fn codegen_inline_asm<'tcx>(
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crate::trap::trap_unimplemented(fx, "Alloca is not supported");
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}
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let mut slot_size = Size::from_bytes(0);
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let mut clobbered_regs = Vec::new();
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let mut inputs = Vec::new();
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let mut outputs = Vec::new();
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let mut new_slot = |reg_class: InlineAsmRegClass| {
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let reg_size = reg_class
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.supported_types(InlineAsmArch::X86_64)
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.iter()
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.map(|(ty, _)| ty.size())
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.max()
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.unwrap();
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let align = rustc_target::abi::Align::from_bytes(reg_size.bytes()).unwrap();
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slot_size = slot_size.align_to(align);
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let offset = slot_size;
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slot_size += reg_size;
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offset
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let mut asm_gen = InlineAssemblyGenerator {
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tcx: fx.tcx,
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arch: fx.tcx.sess.asm_arch.unwrap(),
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template,
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operands,
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options,
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registers: Vec::new(),
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stack_slots_clobber: Vec::new(),
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stack_slots_input: Vec::new(),
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stack_slots_output: Vec::new(),
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stack_slot_size: Size::from_bytes(0),
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};
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asm_gen.allocate_registers();
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asm_gen.allocate_stack_slots();
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// FIXME overlap input and output slots to save stack space
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for operand in operands {
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let inline_asm_index = fx.inline_asm_index;
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fx.inline_asm_index += 1;
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let asm_name = format!("{}__inline_asm_{}", fx.symbol_name, inline_asm_index);
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let generated_asm = asm_gen.generate_asm_wrapper(&asm_name);
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fx.cx.global_asm.push_str(&generated_asm);
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for (i, operand) in operands.iter().enumerate() {
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match *operand {
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InlineAsmOperand::In { reg, ref value } => {
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let reg = expect_reg(reg);
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clobbered_regs.push((reg, new_slot(reg.reg_class())));
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InlineAsmOperand::In { reg: _, ref value } => {
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inputs.push((
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reg,
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new_slot(reg.reg_class()),
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asm_gen.stack_slots_input[i].unwrap(),
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crate::base::codegen_operand(fx, value).load_scalar(fx),
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));
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}
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InlineAsmOperand::Out { reg, late: _, place } => {
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let reg = expect_reg(reg);
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clobbered_regs.push((reg, new_slot(reg.reg_class())));
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InlineAsmOperand::Out { reg: _, late: _, place } => {
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if let Some(place) = place {
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outputs.push((
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reg,
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new_slot(reg.reg_class()),
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asm_gen.stack_slots_output[i].unwrap(),
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crate::base::codegen_place(fx, place),
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));
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}
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}
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InlineAsmOperand::InOut { reg, late: _, ref in_value, out_place } => {
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let reg = expect_reg(reg);
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clobbered_regs.push((reg, new_slot(reg.reg_class())));
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InlineAsmOperand::InOut { reg: _, late: _, ref in_value, out_place } => {
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inputs.push((
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reg,
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new_slot(reg.reg_class()),
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asm_gen.stack_slots_input[i].unwrap(),
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crate::base::codegen_operand(fx, in_value).load_scalar(fx),
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));
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if let Some(out_place) = out_place {
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outputs.push((
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reg,
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new_slot(reg.reg_class()),
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asm_gen.stack_slots_output[i].unwrap(),
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crate::base::codegen_place(fx, out_place),
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));
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}
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@ -160,106 +162,467 @@ pub(crate) fn codegen_inline_asm<'tcx>(
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}
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}
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let inline_asm_index = fx.inline_asm_index;
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fx.inline_asm_index += 1;
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let asm_name = format!("{}__inline_asm_{}", fx.symbol_name, inline_asm_index);
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let generated_asm = generate_asm_wrapper(
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&asm_name,
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InlineAsmArch::X86_64,
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options,
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template,
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clobbered_regs,
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&inputs,
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&outputs,
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);
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fx.cx.global_asm.push_str(&generated_asm);
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call_inline_asm(fx, &asm_name, slot_size, inputs, outputs);
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call_inline_asm(fx, &asm_name, asm_gen.stack_slot_size, inputs, outputs);
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}
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fn generate_asm_wrapper(
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asm_name: &str,
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struct InlineAssemblyGenerator<'a, 'tcx> {
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tcx: TyCtxt<'tcx>,
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arch: InlineAsmArch,
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template: &'a [InlineAsmTemplatePiece],
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operands: &'a [InlineAsmOperand<'tcx>],
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options: InlineAsmOptions,
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template: &[InlineAsmTemplatePiece],
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clobbered_regs: Vec<(InlineAsmReg, Size)>,
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inputs: &[(InlineAsmReg, Size, Value)],
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outputs: &[(InlineAsmReg, Size, CPlace<'_>)],
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) -> String {
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let mut generated_asm = String::new();
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writeln!(generated_asm, ".globl {}", asm_name).unwrap();
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writeln!(generated_asm, ".type {},@function", asm_name).unwrap();
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writeln!(generated_asm, ".section .text.{},\"ax\",@progbits", asm_name).unwrap();
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writeln!(generated_asm, "{}:", asm_name).unwrap();
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registers: Vec<Option<InlineAsmReg>>,
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stack_slots_clobber: Vec<Option<Size>>,
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stack_slots_input: Vec<Option<Size>>,
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stack_slots_output: Vec<Option<Size>>,
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stack_slot_size: Size,
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}
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generated_asm.push_str(".intel_syntax noprefix\n");
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generated_asm.push_str(" push rbp\n");
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generated_asm.push_str(" mov rbp,rdi\n");
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impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> {
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fn allocate_registers(&mut self) {
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let sess = self.tcx.sess;
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let map = allocatable_registers(
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self.arch,
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|feature| sess.target_features.contains(&Symbol::intern(feature)),
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&sess.target,
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);
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let mut allocated = FxHashMap::<_, (bool, bool)>::default();
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let mut regs = vec![None; self.operands.len()];
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// Save clobbered registers
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if !options.contains(InlineAsmOptions::NORETURN) {
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// FIXME skip registers saved by the calling convention
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for &(reg, offset) in &clobbered_regs {
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save_register(&mut generated_asm, arch, reg, offset);
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}
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}
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// Write input registers
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for &(reg, offset, _value) in inputs {
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restore_register(&mut generated_asm, arch, reg, offset);
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}
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if options.contains(InlineAsmOptions::ATT_SYNTAX) {
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generated_asm.push_str(".att_syntax\n");
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}
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// The actual inline asm
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for piece in template {
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match piece {
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InlineAsmTemplatePiece::String(s) => {
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generated_asm.push_str(s);
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// Add explicit registers to the allocated set.
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for (i, operand) in self.operands.iter().enumerate() {
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match *operand {
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InlineAsmOperand::In { reg: InlineAsmRegOrRegClass::Reg(reg), .. } => {
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regs[i] = Some(reg);
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allocated.entry(reg).or_default().0 = true;
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}
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InlineAsmOperand::Out {
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reg: InlineAsmRegOrRegClass::Reg(reg), late: true, ..
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} => {
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regs[i] = Some(reg);
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allocated.entry(reg).or_default().1 = true;
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}
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InlineAsmOperand::Out { reg: InlineAsmRegOrRegClass::Reg(reg), .. }
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| InlineAsmOperand::InOut { reg: InlineAsmRegOrRegClass::Reg(reg), .. } => {
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regs[i] = Some(reg);
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allocated.insert(reg, (true, true));
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}
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_ => (),
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}
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InlineAsmTemplatePiece::Placeholder { operand_idx: _, modifier: _, span: _ } => todo!(),
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}
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}
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generated_asm.push('\n');
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if options.contains(InlineAsmOptions::ATT_SYNTAX) {
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generated_asm.push_str(".intel_syntax noprefix\n");
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}
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if !options.contains(InlineAsmOptions::NORETURN) {
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// Read output registers
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for &(reg, offset, _place) in outputs {
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save_register(&mut generated_asm, arch, reg, offset);
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}
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// Restore clobbered registers
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for &(reg, offset) in clobbered_regs.iter().rev() {
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restore_register(&mut generated_asm, arch, reg, offset);
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// Allocate out/inout/inlateout registers first because they are more constrained.
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for (i, operand) in self.operands.iter().enumerate() {
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match *operand {
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InlineAsmOperand::Out {
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reg: InlineAsmRegOrRegClass::RegClass(class),
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late: false,
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..
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}
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| InlineAsmOperand::InOut {
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reg: InlineAsmRegOrRegClass::RegClass(class), ..
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} => {
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let mut alloc_reg = None;
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for ® in &map[&class] {
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let mut used = false;
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reg.overlapping_regs(|r| {
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if allocated.contains_key(&r) {
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used = true;
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}
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});
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if !used {
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alloc_reg = Some(reg);
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break;
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}
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}
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let reg = alloc_reg.expect("cannot allocate registers");
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regs[i] = Some(reg);
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allocated.insert(reg, (true, true));
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}
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_ => (),
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}
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}
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generated_asm.push_str(" pop rbp\n");
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generated_asm.push_str(" ret\n");
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} else {
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generated_asm.push_str(" ud2\n");
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// Allocate in/lateout.
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for (i, operand) in self.operands.iter().enumerate() {
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match *operand {
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InlineAsmOperand::In { reg: InlineAsmRegOrRegClass::RegClass(class), .. } => {
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let mut alloc_reg = None;
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for ® in &map[&class] {
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let mut used = false;
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reg.overlapping_regs(|r| {
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if allocated.get(&r).copied().unwrap_or_default().0 {
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used = true;
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}
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});
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if !used {
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alloc_reg = Some(reg);
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break;
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}
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}
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let reg = alloc_reg.expect("cannot allocate registers");
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regs[i] = Some(reg);
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allocated.entry(reg).or_default().0 = true;
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}
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InlineAsmOperand::Out {
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reg: InlineAsmRegOrRegClass::RegClass(class),
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late: true,
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..
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} => {
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let mut alloc_reg = None;
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for ® in &map[&class] {
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let mut used = false;
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reg.overlapping_regs(|r| {
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if allocated.get(&r).copied().unwrap_or_default().1 {
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used = true;
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}
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});
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if !used {
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alloc_reg = Some(reg);
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break;
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}
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}
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let reg = alloc_reg.expect("cannot allocate registers");
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regs[i] = Some(reg);
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allocated.entry(reg).or_default().1 = true;
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}
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_ => (),
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}
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}
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self.registers = regs;
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}
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generated_asm.push_str(".att_syntax\n");
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writeln!(generated_asm, ".size {name}, .-{name}", name = asm_name).unwrap();
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generated_asm.push_str(".text\n");
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generated_asm.push_str("\n\n");
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fn allocate_stack_slots(&mut self) {
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let mut slot_size = Size::from_bytes(0);
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let mut slots_clobber = vec![None; self.operands.len()];
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let mut slots_input = vec![None; self.operands.len()];
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let mut slots_output = vec![None; self.operands.len()];
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generated_asm
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let new_slot_fn = |slot_size: &mut Size, reg_class: InlineAsmRegClass| {
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let reg_size =
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reg_class.supported_types(self.arch).iter().map(|(ty, _)| ty.size()).max().unwrap();
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let align = rustc_target::abi::Align::from_bytes(reg_size.bytes()).unwrap();
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let offset = slot_size.align_to(align);
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*slot_size = offset + reg_size;
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offset
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};
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let mut new_slot = |x| new_slot_fn(&mut slot_size, x);
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// Allocate stack slots for saving clobbered registers
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let abi_clobber =
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InlineAsmClobberAbi::parse(self.arch, &self.tcx.sess.target, Symbol::intern("C"))
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.unwrap()
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.clobbered_regs();
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for (i, reg) in self.registers.iter().enumerate().filter_map(|(i, r)| r.map(|r| (i, r))) {
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let mut need_save = true;
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// If the register overlaps with a register clobbered by function call, then
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// we don't need to save it.
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for r in abi_clobber {
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r.overlapping_regs(|r| {
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if r == reg {
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need_save = false;
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}
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});
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if !need_save {
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break;
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}
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}
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if need_save {
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slots_clobber[i] = Some(new_slot(reg.reg_class()));
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}
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}
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// Allocate stack slots for inout
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for (i, operand) in self.operands.iter().enumerate() {
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match *operand {
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InlineAsmOperand::InOut { reg, out_place: Some(_), .. } => {
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let slot = new_slot(reg.reg_class());
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slots_input[i] = Some(slot);
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slots_output[i] = Some(slot);
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}
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_ => (),
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}
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}
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let slot_size_before_input = slot_size;
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let mut new_slot = |x| new_slot_fn(&mut slot_size, x);
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// Allocate stack slots for input
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for (i, operand) in self.operands.iter().enumerate() {
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match *operand {
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InlineAsmOperand::In { reg, .. }
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| InlineAsmOperand::InOut { reg, out_place: None, .. } => {
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slots_input[i] = Some(new_slot(reg.reg_class()));
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}
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_ => (),
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}
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}
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// Reset slot size to before input so that input and output operands can overlap
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// and save some memory.
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let slot_size_after_input = slot_size;
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slot_size = slot_size_before_input;
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let mut new_slot = |x| new_slot_fn(&mut slot_size, x);
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// Allocate stack slots for output
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for (i, operand) in self.operands.iter().enumerate() {
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match *operand {
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InlineAsmOperand::Out { reg, place: Some(_), .. } => {
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slots_output[i] = Some(new_slot(reg.reg_class()));
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}
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_ => (),
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}
|
||||
}
|
||||
|
||||
slot_size = slot_size.max(slot_size_after_input);
|
||||
|
||||
self.stack_slots_clobber = slots_clobber;
|
||||
self.stack_slots_input = slots_input;
|
||||
self.stack_slots_output = slots_output;
|
||||
self.stack_slot_size = slot_size;
|
||||
}
|
||||
|
||||
fn generate_asm_wrapper(&self, asm_name: &str) -> String {
|
||||
let mut generated_asm = String::new();
|
||||
writeln!(generated_asm, ".globl {}", asm_name).unwrap();
|
||||
writeln!(generated_asm, ".type {},@function", asm_name).unwrap();
|
||||
writeln!(generated_asm, ".section .text.{},\"ax\",@progbits", asm_name).unwrap();
|
||||
writeln!(generated_asm, "{}:", asm_name).unwrap();
|
||||
|
||||
let is_x86 = matches!(self.arch, InlineAsmArch::X86 | InlineAsmArch::X86_64);
|
||||
|
||||
if is_x86 {
|
||||
generated_asm.push_str(".intel_syntax noprefix\n");
|
||||
}
|
||||
Self::prologue(&mut generated_asm, self.arch);
|
||||
|
||||
// Save clobbered registers
|
||||
if !self.options.contains(InlineAsmOptions::NORETURN) {
|
||||
for (reg, slot) in self
|
||||
.registers
|
||||
.iter()
|
||||
.zip(self.stack_slots_clobber.iter().copied())
|
||||
.filter_map(|(r, s)| r.zip(s))
|
||||
{
|
||||
Self::save_register(&mut generated_asm, self.arch, reg, slot);
|
||||
}
|
||||
}
|
||||
|
||||
// Write input registers
|
||||
for (reg, slot) in self
|
||||
.registers
|
||||
.iter()
|
||||
.zip(self.stack_slots_input.iter().copied())
|
||||
.filter_map(|(r, s)| r.zip(s))
|
||||
{
|
||||
Self::restore_register(&mut generated_asm, self.arch, reg, slot);
|
||||
}
|
||||
|
||||
if is_x86 && self.options.contains(InlineAsmOptions::ATT_SYNTAX) {
|
||||
generated_asm.push_str(".att_syntax\n");
|
||||
}
|
||||
|
||||
// The actual inline asm
|
||||
for piece in self.template {
|
||||
match piece {
|
||||
InlineAsmTemplatePiece::String(s) => {
|
||||
generated_asm.push_str(s);
|
||||
}
|
||||
InlineAsmTemplatePiece::Placeholder { operand_idx, modifier, span: _ } => {
|
||||
if self.options.contains(InlineAsmOptions::ATT_SYNTAX) {
|
||||
generated_asm.push('%');
|
||||
}
|
||||
self.registers[*operand_idx]
|
||||
.unwrap()
|
||||
.emit(&mut generated_asm, self.arch, *modifier)
|
||||
.unwrap();
|
||||
}
|
||||
}
|
||||
}
|
||||
generated_asm.push('\n');
|
||||
|
||||
if is_x86 && self.options.contains(InlineAsmOptions::ATT_SYNTAX) {
|
||||
generated_asm.push_str(".intel_syntax noprefix\n");
|
||||
}
|
||||
|
||||
if !self.options.contains(InlineAsmOptions::NORETURN) {
|
||||
// Read output registers
|
||||
for (reg, slot) in self
|
||||
.registers
|
||||
.iter()
|
||||
.zip(self.stack_slots_output.iter().copied())
|
||||
.filter_map(|(r, s)| r.zip(s))
|
||||
{
|
||||
Self::save_register(&mut generated_asm, self.arch, reg, slot);
|
||||
}
|
||||
|
||||
// Restore clobbered registers
|
||||
for (reg, slot) in self
|
||||
.registers
|
||||
.iter()
|
||||
.zip(self.stack_slots_clobber.iter().copied())
|
||||
.filter_map(|(r, s)| r.zip(s))
|
||||
{
|
||||
Self::restore_register(&mut generated_asm, self.arch, reg, slot);
|
||||
}
|
||||
|
||||
Self::epilogue(&mut generated_asm, self.arch);
|
||||
} else {
|
||||
Self::epilogue_noreturn(&mut generated_asm, self.arch);
|
||||
}
|
||||
|
||||
if is_x86 {
|
||||
generated_asm.push_str(".att_syntax\n");
|
||||
}
|
||||
writeln!(generated_asm, ".size {name}, .-{name}", name = asm_name).unwrap();
|
||||
generated_asm.push_str(".text\n");
|
||||
generated_asm.push_str("\n\n");
|
||||
|
||||
generated_asm
|
||||
}
|
||||
|
||||
fn prologue(generated_asm: &mut String, arch: InlineAsmArch) {
|
||||
match arch {
|
||||
InlineAsmArch::X86 => {
|
||||
generated_asm.push_str(" push ebp\n");
|
||||
generated_asm.push_str(" mov ebp,[esp+8]\n");
|
||||
}
|
||||
InlineAsmArch::X86_64 => {
|
||||
generated_asm.push_str(" push rbp\n");
|
||||
generated_asm.push_str(" mov rbp,rdi\n");
|
||||
}
|
||||
InlineAsmArch::RiscV32 => {
|
||||
generated_asm.push_str(" addi sp, sp, -8\n");
|
||||
generated_asm.push_str(" sw ra, 4(sp)\n");
|
||||
generated_asm.push_str(" sw s0, 0(sp)\n");
|
||||
generated_asm.push_str(" mv s0, a0\n");
|
||||
}
|
||||
InlineAsmArch::RiscV64 => {
|
||||
generated_asm.push_str(" addi sp, sp, -16\n");
|
||||
generated_asm.push_str(" sd ra, 8(sp)\n");
|
||||
generated_asm.push_str(" sd s0, 0(sp)\n");
|
||||
generated_asm.push_str(" mv s0, a0\n");
|
||||
}
|
||||
_ => unimplemented!("prologue for {:?}", arch),
|
||||
}
|
||||
}
|
||||
|
||||
fn epilogue(generated_asm: &mut String, arch: InlineAsmArch) {
|
||||
match arch {
|
||||
InlineAsmArch::X86 => {
|
||||
generated_asm.push_str(" pop ebp\n");
|
||||
generated_asm.push_str(" ret\n");
|
||||
}
|
||||
InlineAsmArch::X86_64 => {
|
||||
generated_asm.push_str(" pop rbp\n");
|
||||
generated_asm.push_str(" ret\n");
|
||||
}
|
||||
InlineAsmArch::RiscV32 => {
|
||||
generated_asm.push_str(" lw s0, 0(sp)\n");
|
||||
generated_asm.push_str(" lw ra, 4(sp)\n");
|
||||
generated_asm.push_str(" addi sp, sp, 8\n");
|
||||
generated_asm.push_str(" ret\n");
|
||||
}
|
||||
InlineAsmArch::RiscV64 => {
|
||||
generated_asm.push_str(" ld s0, 0(sp)\n");
|
||||
generated_asm.push_str(" ld ra, 8(sp)\n");
|
||||
generated_asm.push_str(" addi sp, sp, 16\n");
|
||||
generated_asm.push_str(" ret\n");
|
||||
}
|
||||
_ => unimplemented!("epilogue for {:?}", arch),
|
||||
}
|
||||
}
|
||||
|
||||
fn epilogue_noreturn(generated_asm: &mut String, arch: InlineAsmArch) {
|
||||
match arch {
|
||||
InlineAsmArch::X86 | InlineAsmArch::X86_64 => {
|
||||
generated_asm.push_str(" ud2\n");
|
||||
}
|
||||
InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {
|
||||
generated_asm.push_str(" ebreak\n");
|
||||
}
|
||||
_ => unimplemented!("epilogue_noreturn for {:?}", arch),
|
||||
}
|
||||
}
|
||||
|
||||
fn save_register(
|
||||
generated_asm: &mut String,
|
||||
arch: InlineAsmArch,
|
||||
reg: InlineAsmReg,
|
||||
offset: Size,
|
||||
) {
|
||||
match arch {
|
||||
InlineAsmArch::X86 => {
|
||||
write!(generated_asm, " mov [ebp+0x{:x}], ", offset.bytes()).unwrap();
|
||||
reg.emit(generated_asm, InlineAsmArch::X86, None).unwrap();
|
||||
generated_asm.push('\n');
|
||||
}
|
||||
InlineAsmArch::X86_64 => {
|
||||
write!(generated_asm, " mov [rbp+0x{:x}], ", offset.bytes()).unwrap();
|
||||
reg.emit(generated_asm, InlineAsmArch::X86_64, None).unwrap();
|
||||
generated_asm.push('\n');
|
||||
}
|
||||
InlineAsmArch::RiscV32 => {
|
||||
generated_asm.push_str(" sw ");
|
||||
reg.emit(generated_asm, InlineAsmArch::RiscV32, None).unwrap();
|
||||
writeln!(generated_asm, ", 0x{:x}(s0)", offset.bytes()).unwrap();
|
||||
}
|
||||
InlineAsmArch::RiscV64 => {
|
||||
generated_asm.push_str(" sd ");
|
||||
reg.emit(generated_asm, InlineAsmArch::RiscV64, None).unwrap();
|
||||
writeln!(generated_asm, ", 0x{:x}(s0)", offset.bytes()).unwrap();
|
||||
}
|
||||
_ => unimplemented!("save_register for {:?}", arch),
|
||||
}
|
||||
}
|
||||
|
||||
fn restore_register(
|
||||
generated_asm: &mut String,
|
||||
arch: InlineAsmArch,
|
||||
reg: InlineAsmReg,
|
||||
offset: Size,
|
||||
) {
|
||||
match arch {
|
||||
InlineAsmArch::X86 => {
|
||||
generated_asm.push_str(" mov ");
|
||||
reg.emit(generated_asm, InlineAsmArch::X86, None).unwrap();
|
||||
writeln!(generated_asm, ", [ebp+0x{:x}]", offset.bytes()).unwrap();
|
||||
}
|
||||
InlineAsmArch::X86_64 => {
|
||||
generated_asm.push_str(" mov ");
|
||||
reg.emit(generated_asm, InlineAsmArch::X86_64, None).unwrap();
|
||||
writeln!(generated_asm, ", [rbp+0x{:x}]", offset.bytes()).unwrap();
|
||||
}
|
||||
InlineAsmArch::RiscV32 => {
|
||||
generated_asm.push_str(" lw ");
|
||||
reg.emit(generated_asm, InlineAsmArch::RiscV32, None).unwrap();
|
||||
writeln!(generated_asm, ", 0x{:x}(s0)", offset.bytes()).unwrap();
|
||||
}
|
||||
InlineAsmArch::RiscV64 => {
|
||||
generated_asm.push_str(" ld ");
|
||||
reg.emit(generated_asm, InlineAsmArch::RiscV64, None).unwrap();
|
||||
writeln!(generated_asm, ", 0x{:x}(s0)", offset.bytes()).unwrap();
|
||||
}
|
||||
_ => unimplemented!("restore_register for {:?}", arch),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
fn call_inline_asm<'tcx>(
|
||||
fx: &mut FunctionCx<'_, '_, 'tcx>,
|
||||
asm_name: &str,
|
||||
slot_size: Size,
|
||||
inputs: Vec<(InlineAsmReg, Size, Value)>,
|
||||
outputs: Vec<(InlineAsmReg, Size, CPlace<'tcx>)>,
|
||||
inputs: Vec<(Size, Value)>,
|
||||
outputs: Vec<(Size, CPlace<'tcx>)>,
|
||||
) {
|
||||
let stack_slot = fx.bcx.func.create_stack_slot(StackSlotData {
|
||||
kind: StackSlotKind::ExplicitSlot,
|
||||
|
|
@ -286,50 +649,16 @@ fn call_inline_asm<'tcx>(
|
|||
fx.add_comment(inline_asm_func, asm_name);
|
||||
}
|
||||
|
||||
for (_reg, offset, value) in inputs {
|
||||
for (offset, value) in inputs {
|
||||
fx.bcx.ins().stack_store(value, stack_slot, i32::try_from(offset.bytes()).unwrap());
|
||||
}
|
||||
|
||||
let stack_slot_addr = fx.bcx.ins().stack_addr(fx.pointer_type, stack_slot, 0);
|
||||
fx.bcx.ins().call(inline_asm_func, &[stack_slot_addr]);
|
||||
|
||||
for (_reg, offset, place) in outputs {
|
||||
for (offset, place) in outputs {
|
||||
let ty = fx.clif_type(place.layout().ty).unwrap();
|
||||
let value = fx.bcx.ins().stack_load(ty, stack_slot, i32::try_from(offset.bytes()).unwrap());
|
||||
place.write_cvalue(fx, CValue::by_val(value, place.layout()));
|
||||
}
|
||||
}
|
||||
|
||||
fn expect_reg(reg_or_class: InlineAsmRegOrRegClass) -> InlineAsmReg {
|
||||
match reg_or_class {
|
||||
InlineAsmRegOrRegClass::Reg(reg) => reg,
|
||||
InlineAsmRegOrRegClass::RegClass(class) => unimplemented!("{:?}", class),
|
||||
}
|
||||
}
|
||||
|
||||
fn save_register(generated_asm: &mut String, arch: InlineAsmArch, reg: InlineAsmReg, offset: Size) {
|
||||
match arch {
|
||||
InlineAsmArch::X86_64 => {
|
||||
write!(generated_asm, " mov [rbp+0x{:x}], ", offset.bytes()).unwrap();
|
||||
reg.emit(generated_asm, InlineAsmArch::X86_64, None).unwrap();
|
||||
generated_asm.push('\n');
|
||||
}
|
||||
_ => unimplemented!("save_register for {:?}", arch),
|
||||
}
|
||||
}
|
||||
|
||||
fn restore_register(
|
||||
generated_asm: &mut String,
|
||||
arch: InlineAsmArch,
|
||||
reg: InlineAsmReg,
|
||||
offset: Size,
|
||||
) {
|
||||
match arch {
|
||||
InlineAsmArch::X86_64 => {
|
||||
generated_asm.push_str(" mov ");
|
||||
reg.emit(generated_asm, InlineAsmArch::X86_64, None).unwrap();
|
||||
writeln!(generated_asm, ", [rbp+0x{:x}]", offset.bytes()).unwrap();
|
||||
}
|
||||
_ => unimplemented!("restore_register for {:?}", arch),
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue