8da494272f
Fixes #72386 This type also needs to get allocated on the `librustc_middle` arena when we deserialize MIR.
22 lines
403 B
Rust
22 lines
403 B
Rust
// revisions: rpass1 cfail1 rpass3
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// only-x86_64
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// Regression test for issue #72386
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// Checks that we don't ICE when switching to an invalid register
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// and back again
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#![feature(asm)]
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#[cfg(any(rpass1, rpass3))]
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fn main() {
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unsafe {
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asm!("nop")
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}
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}
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#[cfg(cfail1)]
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fn main() {
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unsafe {
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asm!("nop",out("invalid_reg")_)
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//[cfail1]~^ ERROR invalid register
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}
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}
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