os-rust/tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_smaller.PreCodegen.after.mir

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// MIR for `unchecked_shl_unsigned_smaller` after PreCodegen
fn unchecked_shl_unsigned_smaller(_1: u16, _2: u32) -> u16 {
debug a => _1; // in scope 0 at $DIR/unchecked_shifts.rs:+0:46: +0:47
debug b => _2; // in scope 0 at $DIR/unchecked_shifts.rs:+0:54: +0:55
let mut _0: u16; // return place in scope 0 at $DIR/unchecked_shifts.rs:+0:65: +0:68
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scope 1 (inlined core::num::<impl u16>::unchecked_shl) { // at $DIR/unchecked_shifts.rs:11:7: 11:23
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debug self => _1; // in scope 1 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
debug rhs => _2; // in scope 1 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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let mut _3: u16; // in scope 1 at $SRC_DIR/core/src/num/mod.rs:LL:COL
let mut _4: (u32,); // in scope 1 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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scope 2 {
}
}
bb0: {
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StorageLive(_3); // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
StorageLive(_4); // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
_4 = (_2,); // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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_3 = core::num::<impl u16>::unchecked_shl::conv(move (_4.0: u32)) -> bb1; // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
// mir::Constant
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// + span: $SRC_DIR/core/src/num/mod.rs:LL:COL
// + literal: Const { ty: fn(u32) -> u16 {core::num::<impl u16>::unchecked_shl::conv}, val: Value(<ZST>) }
}
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bb1: {
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StorageDead(_4); // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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_0 = unchecked_shl::<u16>(_1, move _3) -> [return: bb2, unwind unreachable]; // scope 2 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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// mir::Constant
// + span: $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
// + literal: Const { ty: unsafe extern "rust-intrinsic" fn(u16, u16) -> u16 {unchecked_shl::<u16>}, val: Value(<ZST>) }
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}
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bb2: {
StorageDead(_3); // scope 2 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
return; // scope 0 at $DIR/unchecked_shifts.rs:+2:2: +2:2
}
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}