Implement AST lowering for asm!
This commit is contained in:
Amanieu d'Antras
parent
d5b1501d8c
commit
ec1ad61f88
4 changed files with 320 additions and 6 deletions
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@ -3,6 +3,7 @@ use super::{ImplTraitContext, LoweringContext, ParamMode, ParenthesizedGenericAr
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use rustc_ast::ast::*;
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use rustc_ast::attr;
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use rustc_ast::ptr::P as AstP;
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use rustc_data_structures::fx::FxHashMap;
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use rustc_data_structures::stack::ensure_sufficient_stack;
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use rustc_data_structures::thin_vec::ThinVec;
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use rustc_errors::struct_span_err;
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@ -10,6 +11,9 @@ use rustc_hir as hir;
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use rustc_hir::def::Res;
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use rustc_span::source_map::{respan, DesugaringKind, Span, Spanned};
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use rustc_span::symbol::{sym, Ident, Symbol};
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use rustc_target::asm;
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use std::collections::hash_map::Entry;
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use std::fmt::Write;
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impl<'hir> LoweringContext<'_, 'hir> {
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fn lower_exprs(&mut self, exprs: &[AstP<Expr>]) -> &'hir [hir::Expr<'hir>] {
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@ -175,7 +179,8 @@ impl<'hir> LoweringContext<'_, 'hir> {
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let e = e.as_ref().map(|x| self.lower_expr(x));
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hir::ExprKind::Ret(e)
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}
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ExprKind::LlvmInlineAsm(ref asm) => self.lower_expr_asm(asm),
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ExprKind::InlineAsm(ref asm) => self.lower_expr_asm(e.span, asm),
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ExprKind::LlvmInlineAsm(ref asm) => self.lower_expr_llvm_asm(asm),
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ExprKind::Struct(ref path, ref fields, ref maybe_expr) => {
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let maybe_expr = maybe_expr.as_ref().map(|x| self.lower_expr(x));
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hir::ExprKind::Struct(
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@ -968,7 +973,294 @@ impl<'hir> LoweringContext<'_, 'hir> {
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result
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}
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fn lower_expr_asm(&mut self, asm: &LlvmInlineAsm) -> hir::ExprKind<'hir> {
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fn lower_expr_asm(&mut self, sp: Span, asm: &InlineAsm) -> hir::ExprKind<'hir> {
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let asm_arch = if let Some(asm_arch) = self.sess.asm_arch {
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asm_arch
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} else {
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struct_span_err!(self.sess, sp, E0472, "asm! is unsupported on this target").emit();
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return hir::ExprKind::Err;
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};
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// Lower operands to HIR, filter_map skips any operands with invalid
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// register classes.
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let sess = self.sess;
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let operands: Vec<_> = asm
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.operands
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.iter()
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.filter_map(|(op, op_sp)| {
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let lower_reg = |reg| {
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Some(match reg {
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InlineAsmRegOrRegClass::Reg(s) => asm::InlineAsmRegOrRegClass::Reg(
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asm::InlineAsmReg::parse(
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asm_arch,
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|feature| {
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self.sess.target_features.contains(&Symbol::intern(feature))
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},
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s,
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)
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.map_err(|e| {
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let msg = format!("invalid register `{}`: {}", s.as_str(), e);
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sess.struct_span_err(*op_sp, &msg).emit();
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})
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.ok()?,
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),
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InlineAsmRegOrRegClass::RegClass(s) => {
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asm::InlineAsmRegOrRegClass::RegClass(
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asm::InlineAsmRegClass::parse(asm_arch, s)
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.map_err(|e| {
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let msg = format!(
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"invalid register class `{}`: {}",
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s.as_str(),
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e
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);
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sess.struct_span_err(*op_sp, &msg).emit();
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})
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.ok()?,
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)
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}
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})
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};
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let op = match op {
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InlineAsmOperand::In { reg, expr } => hir::InlineAsmOperand::In {
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reg: lower_reg(*reg)?,
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expr: self.lower_expr_mut(expr),
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},
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InlineAsmOperand::Out { reg, late, expr } => hir::InlineAsmOperand::Out {
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reg: lower_reg(*reg)?,
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late: *late,
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expr: expr.as_ref().map(|expr| self.lower_expr_mut(expr)),
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},
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InlineAsmOperand::InOut { reg, late, expr } => hir::InlineAsmOperand::InOut {
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reg: lower_reg(*reg)?,
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late: *late,
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expr: self.lower_expr_mut(expr),
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},
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InlineAsmOperand::SplitInOut { reg, late, in_expr, out_expr } => {
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hir::InlineAsmOperand::SplitInOut {
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reg: lower_reg(*reg)?,
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late: *late,
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in_expr: self.lower_expr_mut(in_expr),
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out_expr: out_expr.as_ref().map(|expr| self.lower_expr_mut(expr)),
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}
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}
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InlineAsmOperand::Const { expr } => {
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hir::InlineAsmOperand::Const { expr: self.lower_expr_mut(expr) }
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}
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InlineAsmOperand::Sym { expr } => {
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hir::InlineAsmOperand::Sym { expr: self.lower_expr_mut(expr) }
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}
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};
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Some(op)
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})
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.collect();
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// Stop if there were any errors when lowering the register classes
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if operands.len() != asm.operands.len() {
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return hir::ExprKind::Err;
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}
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// Validate template modifiers against the register classes for the operands
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for p in &asm.template {
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if let asm::InlineAsmTemplatePiece::Placeholder {
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operand_idx,
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modifier: Some(modifier),
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span: placeholder_span,
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} = *p
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{
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let op_sp = asm.operands[operand_idx].1;
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match &operands[operand_idx] {
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hir::InlineAsmOperand::In { reg, .. }
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| hir::InlineAsmOperand::Out { reg, .. }
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| hir::InlineAsmOperand::InOut { reg, .. }
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| hir::InlineAsmOperand::SplitInOut { reg, .. } => {
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let class = reg.reg_class();
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let valid_modifiers = class.valid_modifiers(asm_arch);
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if !valid_modifiers.contains(&modifier) {
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let mut err = sess.struct_span_err(
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placeholder_span,
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"invalid asm template modifier for this register class",
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);
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err.span_label(placeholder_span, "template modifier");
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err.span_label(op_sp, "argument");
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if !valid_modifiers.is_empty() {
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let mut mods = format!("`{}`", valid_modifiers[0]);
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for m in &valid_modifiers[1..] {
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let _ = write!(mods, ", `{}`", m);
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}
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err.note(&format!(
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"the `{}` register class supports \
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the following template modifiers: {}",
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class.name(),
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mods
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));
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} else {
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err.note(&format!(
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"the `{}` register class does not support template modifiers",
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class.name()
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));
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}
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err.emit();
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}
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}
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hir::InlineAsmOperand::Const { .. } => {
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let mut err = sess.struct_span_err(
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placeholder_span,
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"asm template modifiers are not allowed for `const` arguments",
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);
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err.span_label(placeholder_span, "template modifier");
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err.span_label(op_sp, "argument");
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err.emit();
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}
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hir::InlineAsmOperand::Sym { .. } => {
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let mut err = sess.struct_span_err(
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placeholder_span,
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"asm template modifiers are not allowed for `sym` arguments",
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);
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err.span_label(placeholder_span, "template modifier");
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err.span_label(op_sp, "argument");
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err.emit();
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}
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}
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}
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}
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let mut used_input_regs = FxHashMap::default();
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let mut used_output_regs = FxHashMap::default();
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for (idx, op) in operands.iter().enumerate() {
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let op_sp = asm.operands[idx].1;
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if let Some(reg) = op.reg() {
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// Validate register classes against currently enabled target
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// features. We check that at least one type is available for
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// the current target.
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let reg_class = reg.reg_class();
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let mut required_features = vec![];
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for &(_, feature) in reg_class.supported_types(asm_arch) {
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if let Some(feature) = feature {
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if self.sess.target_features.contains(&Symbol::intern(feature)) {
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required_features.clear();
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break;
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} else {
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required_features.push(feature);
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}
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} else {
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required_features.clear();
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break;
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}
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}
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required_features.sort();
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required_features.dedup();
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match &required_features[..] {
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[] => {}
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[feature] => {
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let msg = format!(
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"register class `{}` requires the `{}` target feature",
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reg_class.name(),
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feature
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);
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sess.struct_span_err(op_sp, &msg).emit();
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}
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features => {
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let msg = format!(
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"register class `{}` requires at least one target feature: {}",
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reg_class.name(),
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features.join(", ")
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);
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sess.struct_span_err(op_sp, &msg).emit();
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}
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}
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// Check for conflicts between explicit register operands.
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if let asm::InlineAsmRegOrRegClass::Reg(reg) = reg {
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let (input, output) = match op {
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hir::InlineAsmOperand::In { .. } => (true, false),
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// Late output do not conflict with inputs, but normal outputs do
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hir::InlineAsmOperand::Out { late, .. } => (!late, true),
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hir::InlineAsmOperand::InOut { .. }
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| hir::InlineAsmOperand::SplitInOut { .. } => (true, true),
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hir::InlineAsmOperand::Const { .. } | hir::InlineAsmOperand::Sym { .. } => {
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unreachable!()
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}
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};
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// Flag to output the error only once per operand
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let mut skip = false;
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reg.overlapping_regs(|r| {
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let mut check = |used_regs: &mut FxHashMap<asm::InlineAsmReg, usize>,
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input| {
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match used_regs.entry(r) {
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Entry::Occupied(o) => {
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if !skip {
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skip = true;
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let idx2 = *o.get();
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let op2 = &operands[idx2];
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let op_sp2 = asm.operands[idx2].1;
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let reg2 = match op2.reg() {
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Some(asm::InlineAsmRegOrRegClass::Reg(r)) => r,
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_ => unreachable!(),
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};
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let msg = format!(
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"register `{}` conflicts with register `{}`",
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reg.name(),
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reg2.name()
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);
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let mut err = sess.struct_span_err(op_sp, &msg);
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err.span_label(
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op_sp,
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&format!("register `{}`", reg.name()),
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);
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err.span_label(
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op_sp2,
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&format!("register `{}`", reg2.name()),
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);
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match (op, op2) {
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(
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hir::InlineAsmOperand::In { .. },
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hir::InlineAsmOperand::Out { late, .. },
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)
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| (
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hir::InlineAsmOperand::Out { late, .. },
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hir::InlineAsmOperand::In { .. },
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) => {
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assert!(!*late);
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let out_op_sp = if input { op_sp2 } else { op_sp };
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let msg = &format!(
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"use `lateout` instead of \
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`out` to avoid conflict"
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);
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err.span_help(out_op_sp, msg);
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}
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_ => {}
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}
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err.emit();
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}
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}
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Entry::Vacant(v) => {
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v.insert(idx);
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}
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}
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};
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if input {
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check(&mut used_input_regs, true);
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}
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if output {
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check(&mut used_output_regs, false);
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}
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});
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}
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}
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}
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let operands = self.arena.alloc_from_iter(operands);
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let template = self.arena.alloc_from_iter(asm.template.iter().cloned());
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let hir_asm = hir::InlineAsm { template, operands, options: asm.options };
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hir::ExprKind::InlineAsm(self.arena.alloc(hir_asm))
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}
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fn lower_expr_llvm_asm(&mut self, asm: &LlvmInlineAsm) -> hir::ExprKind<'hir> {
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let inner = hir::LlvmInlineAsmInner {
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inputs: asm.inputs.iter().map(|&(c, _)| c).collect(),
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outputs: asm
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@ -14,6 +14,8 @@ macro_rules! arena_types {
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// HIR types
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[few] hir_krate: rustc_hir::Crate<$tcx>,
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[] arm: rustc_hir::Arm<$tcx>,
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[] asm_operand: rustc_hir::InlineAsmOperand<$tcx>,
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[] asm_template: rustc_target::asm::InlineAsmTemplatePiece,
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[] attribute: rustc_ast::ast::Attribute,
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[] block: rustc_hir::Block<$tcx>,
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[] bare_fn_ty: rustc_hir::BareFnTy<$tcx>,
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@ -28,7 +30,8 @@ macro_rules! arena_types {
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[] fn_decl: rustc_hir::FnDecl<$tcx>,
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[] foreign_item: rustc_hir::ForeignItem<$tcx>,
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[] impl_item_ref: rustc_hir::ImplItemRef<$tcx>,
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[] inline_asm: rustc_hir::LlvmInlineAsm<$tcx>,
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[few] inline_asm: rustc_hir::InlineAsm<$tcx>,
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[few] llvm_inline_asm: rustc_hir::LlvmInlineAsm<$tcx>,
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[] local: rustc_hir::Local<$tcx>,
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[few] macro_def: rustc_hir::MacroDef<$tcx>,
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[] param: rustc_hir::Param<$tcx>,
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@ -42,12 +42,15 @@ use std::{panic, thread};
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/// features is available on the target machine, by querying LLVM.
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pub fn add_configuration(
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cfg: &mut CrateConfig,
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sess: &Session,
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sess: &mut Session,
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codegen_backend: &dyn CodegenBackend,
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) {
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let tf = sym::target_feature;
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cfg.extend(codegen_backend.target_features(sess).into_iter().map(|feat| (tf, Some(feat))));
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let target_features = codegen_backend.target_features(sess);
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sess.target_features.extend(target_features.iter().cloned());
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cfg.extend(target_features.into_iter().map(|feat| (tf, Some(feat))));
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if sess.crt_static(None) {
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cfg.insert((tf, Some(Symbol::intern("crt-static"))));
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@ -75,7 +78,7 @@ pub fn create_session(
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let codegen_backend = get_codegen_backend(&sess);
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let mut cfg = config::build_configuration(&sess, config::to_crate_config(cfg));
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add_configuration(&mut cfg, &sess, &*codegen_backend);
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add_configuration(&mut cfg, &mut sess, &*codegen_backend);
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sess.parse_sess.config = cfg;
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(Lrc::new(sess), Lrc::new(codegen_backend), source_map)
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@ -23,6 +23,7 @@ use rustc_errors::{Applicability, DiagnosticBuilder, DiagnosticId, ErrorReported
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use rustc_span::edition::Edition;
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use rustc_span::source_map::{self, FileLoader, MultiSpan, RealFileLoader, SourceMap, Span};
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use rustc_span::{SourceFileHashAlgorithm, Symbol};
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use rustc_target::asm::InlineAsmArch;
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use rustc_target::spec::{CodeModel, PanicStrategy, RelocModel, RelroLevel};
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use rustc_target::spec::{Target, TargetTriple, TlsModel};
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@ -31,6 +32,7 @@ use std::env;
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use std::io::Write;
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use std::num::NonZeroU32;
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use std::path::PathBuf;
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use std::str::FromStr;
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use std::sync::Arc;
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use std::time::Duration;
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@ -158,6 +160,12 @@ pub struct Session {
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/// if Rust was built with path remapping to `/rustc/$hash` enabled
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/// (the `rust.remap-debuginfo` option in `config.toml`).
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pub real_rust_source_base_dir: Option<PathBuf>,
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/// Architecture to use for interpreting asm!.
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pub asm_arch: Option<InlineAsmArch>,
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/// Set of enabled features for the current target.
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pub target_features: FxHashSet<Symbol>,
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}
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pub struct PerfStats {
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@ -1183,6 +1191,12 @@ pub fn build_session_with_source_map(
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if candidate.join("src/libstd/lib.rs").is_file() { Some(candidate) } else { None }
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};
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let asm_arch = if target_cfg.target.options.allow_asm {
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InlineAsmArch::from_str(&target_cfg.target.arch).ok()
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} else {
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None
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};
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let sess = Session {
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target: target_cfg,
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host,
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@ -1223,6 +1237,8 @@ pub fn build_session_with_source_map(
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ctfe_backtrace,
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miri_unleashed_features: Lock::new(Default::default()),
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real_rust_source_base_dir,
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asm_arch,
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target_features: FxHashSet::default(),
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};
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validate_commandline_args_with_session_available(&sess);
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