luojia65 70855b24b8 Add spin_loop hint for RISC-V architecture ... This commit also updates `stdarch` git submodule.		2021-12-05 16:39:21 +08:00
..
benches	Auto merge of #88788 - falk-hueffner:speedup-int-log10-branchless, r=joshtriplett	2021-10-12 03:18:54 +00:00
primitive_docs	Add primitive documentation to libcore	2021-09-12 02:23:08 +00:00
src	Add spin_loop hint for RISC-V architecture	2021-12-05 16:39:21 +08:00
tests	Add a try_reduce method to the Iterator trait	2021-12-04 15:17:14 +11:00
Cargo.toml	rfc3052: Remove authors field from Cargo manifests	2021-07-29 14:56:05 -07:00