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9dd71885d3
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3cc8aa848a
11 changed files with 32 additions and 33 deletions
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@ -18,3 +18,6 @@ spin = "0.9.8"
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[lints.clippy]
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missing_safety_doc = "allow"
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needless_range_loop = "allow"
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type_complexity = "allow"
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upper_case_acronyms = "allow"
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@ -283,7 +283,7 @@ extern "C" {
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}
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fn set_address(entry: &mut IDTEntry, func: unsafe extern "C" fn()) {
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let address = func as u64;
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let address = func as usize as u64;
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entry.address_low = address as u16;
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entry.address_middle = (address >> 16) as u16;
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entry.address_high = (address >> 32) as u32;
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@ -56,7 +56,7 @@ pub fn virt_to_phys(virt: u64) -> u64 {
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assert!(virt >= KERNEL_HEAP_START);
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assert!(virt < KERNEL_HEAP_START + KERNEL_HEAP_INITIAL_SIZE as u64);
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let heap_map = HEAP_PHYS_MAPPING.lock();
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return heap_map[(virt as usize - KERNEL_HEAP_START as usize) / 0x1000] + virt % 0x1000;
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heap_map[(virt as usize - KERNEL_HEAP_START as usize) / 0x1000] + virt % 0x1000
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}
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fn get_table_entry(table: &mut PageTable, i: usize) -> &mut PageTable {
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if table.entries_virt[i].is_none() {
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@ -71,7 +71,7 @@ fn get_table_entry(table: &mut PageTable, i: usize) -> &mut PageTable {
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table.entries_phys[i].set_user(1);
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table.entries_phys[i].set_present(1);
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}
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return table.entries_virt[i].as_mut().unwrap();
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table.entries_virt[i].as_mut().unwrap()
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}
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fn get_page(pml4: &mut PageTable, virt: u64) -> Option<&mut PageEntry> {
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let virt_page = virt as usize / 0x1000;
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@ -147,14 +147,11 @@ pub unsafe fn unmap(address: u64) {
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let mut current_pml4 = CURRENT_PML4.lock();
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let page = get_page(current_pml4.as_mut().unwrap(), address);
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assert!(page.is_some(), "Page isn't mapped");
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match page {
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Some(page) => {
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if let Some(page) = page {
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page.set_present(0);
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page.set_address(0);
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invlpg(address);
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}
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None => {}
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}
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}
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pub unsafe fn map_range(virt_start: u64, phys_start: u64, size: u64, user: bool, write: bool, exec: bool, cache_disable: bool) {
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assert_eq!(virt_start % 0x1000, 0);
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@ -54,7 +54,7 @@ fn copy_to_fb() {
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}
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}
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pub fn display_print(str: &str) {
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if FRAMEBUFFER_ADDR.load(Ordering::SeqCst) == null_mut() {
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if FRAMEBUFFER_ADDR.load(Ordering::SeqCst).is_null() {
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return;
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}
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if INTERRUPTS_SETUP.load(Ordering::SeqCst) {
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@ -42,7 +42,7 @@ extern "C" fn AcpiOsAcquireLock(handle: *mut c_void) -> ACPI_SIZE {
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extern "C" fn AcpiOsAllocate(size: ACPI_SIZE) -> *mut c_void {
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let layout = Layout::from_size_align(size as usize, 16).unwrap();
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unsafe {
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return wrapped_alloc(layout) as *mut c_void;
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wrapped_alloc(layout) as *mut c_void
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}
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}
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#[no_mangle]
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@ -126,7 +126,7 @@ extern "C" fn AcpiOsInstallInterruptHandler(gsi: UINT32, handler: ACPI_OSD_HANDL
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#[no_mangle]
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extern "C" fn AcpiOsMapMemory(phys: ACPI_PHYSICAL_ADDRESS, size: ACPI_SIZE) -> *mut c_void {
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unsafe {
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return map_physical(phys, size, false) as *mut c_void;
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map_physical(phys, size, false) as *mut c_void
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}
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}
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#[no_mangle]
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@ -11,7 +11,7 @@ impl AcpiHandler for EarlyACPIHandler {
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unsafe fn map_physical_region<T>(&self, phys: usize, size: usize) -> PhysicalMapping<Self, T> {
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unsafe {
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let virt = map_physical(phys as u64, size as u64, false);
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return PhysicalMapping::new(phys, NonNull::new(virt as *mut T).unwrap(), size, size, *self);
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PhysicalMapping::new(phys, NonNull::new(virt as *mut T).unwrap(), size, size, *self)
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}
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}
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fn unmap_physical_region<T>(region: &PhysicalMapping<Self, T>) {
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@ -46,7 +46,7 @@ static NEXT_IOAPIC_ID: AtomicUsize = AtomicUsize::new(0);
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fn read_register(apic_i: usize, reg_i: u8) -> u32 {
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unsafe {
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IOAPICS[apic_i].address.load(Ordering::SeqCst).write_volatile(reg_i as u32);
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return IOAPICS[apic_i].address.load(Ordering::SeqCst).add(4).read_volatile();
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IOAPICS[apic_i].address.load(Ordering::SeqCst).add(4).read_volatile()
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}
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}
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fn write_register(apic_i: usize, reg_i: u8, val: u32) {
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@ -57,7 +57,7 @@ fn write_register(apic_i: usize, reg_i: u8, val: u32) {
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}
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fn get_apic_for_gsi(gsi: usize) -> usize {
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for i in 0..NEXT_IOAPIC_ID.load(Ordering::SeqCst) {
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if gsi >= IOAPICS[i].start_gsi.load(Ordering::SeqCst) as usize && gsi < IOAPICS[i].end_gsi.load(Ordering::SeqCst) as usize {
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if gsi >= IOAPICS[i].start_gsi.load(Ordering::SeqCst) && gsi < IOAPICS[i].end_gsi.load(Ordering::SeqCst) {
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return i;
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}
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}
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@ -65,14 +65,14 @@ fn get_apic_for_gsi(gsi: usize) -> usize {
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}
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fn read_redirection(mut gsi: usize) -> RedirectionEntry {
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let apic_i = get_apic_for_gsi(gsi);
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gsi -= IOAPICS[apic_i].start_gsi.load(Ordering::SeqCst) as usize;
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gsi -= IOAPICS[apic_i].start_gsi.load(Ordering::SeqCst);
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let mut redirection_int = read_register(apic_i, REGISTER_REDIRECTION + gsi as u8 * 2) as u64;
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redirection_int |= (read_register(apic_i, REGISTER_REDIRECTION + gsi as u8 * 2 + 1) as u64) << 32;
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return RedirectionEntry(redirection_int);
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RedirectionEntry(redirection_int)
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}
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fn write_redirection(mut gsi: usize, redirection: RedirectionEntry) {
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let apic_i = get_apic_for_gsi(gsi);
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gsi -= IOAPICS[apic_i].start_gsi.load(Ordering::SeqCst) as usize;
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gsi -= IOAPICS[apic_i].start_gsi.load(Ordering::SeqCst);
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write_register(apic_i, REGISTER_REDIRECTION + gsi as u8 * 2, redirection.0 as u32);
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write_register(apic_i, REGISTER_REDIRECTION + gsi as u8 * 2 + 1, (redirection.0 >> 32) as u32);
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}
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@ -94,10 +94,10 @@ pub fn register_irq_handler(vector: usize, handler: fn()) {
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let start = IOAPICS[i].start_gsi.load(Ordering::SeqCst);
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let end = IOAPICS[i].end_gsi.load(Ordering::SeqCst);
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for j in start..end {
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let mut redirection = read_redirection(j as usize);
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let mut redirection = read_redirection(j);
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if redirection.vector() == vector as u64 {
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redirection.set_mask(0);
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write_redirection(j as usize, redirection);
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write_redirection(j, redirection);
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}
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}
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}
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@ -115,6 +115,6 @@ pub fn setup_ioapic(phys: u64, gsi_base: usize) {
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redirection.set_mask(1);
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redirection.set_vector(48 + i as u64);
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redirection.set_destination(BSP_LAPIC_ID.load(Ordering::SeqCst) as u64);
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write_redirection(i as usize, redirection);
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write_redirection(i, redirection);
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}
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}
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@ -36,7 +36,7 @@ impl Spinlock {
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pub fn lock(&self) {
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debug_assert!(INTERRUPTS_SETUP.load(Ordering::SeqCst));
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cli();
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while !self.locked.compare_exchange(false, true, Ordering::SeqCst, Ordering::SeqCst).is_ok() {}
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while self.locked.compare_exchange(false, true, Ordering::SeqCst, Ordering::SeqCst).is_err() {}
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let lapic_id = get_current_lapic_id();
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LOCKS_HELD[lapic_id].fetch_add(1, Ordering::SeqCst);
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self.lapic_id.store(lapic_id, Ordering::SeqCst);
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@ -78,7 +78,7 @@ pub fn switch_task(current_state: &mut ISRState, new_task: Task) {
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}
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pub fn create_task(func: fn()) -> Task {
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let stack = vec![0; STACK_SIZE];
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let task = Task {
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Task {
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id: NEXT_TASK_ID.fetch_add(1, Ordering::SeqCst),
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state: ISRState {
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rax: 0,
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@ -98,7 +98,7 @@ pub fn create_task(func: fn()) -> Task {
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r15: 0,
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isr: 0,
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error_code: 0,
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rip: task_entry as u64,
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rip: task_entry as usize as u64,
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cs: 8,
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rflags: RFLAGS.load(Ordering::SeqCst),
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rsp: stack.as_ptr() as u64 + STACK_SIZE as u64,
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@ -110,8 +110,7 @@ pub fn create_task(func: fn()) -> Task {
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sleep_until_us: 0,
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block_on_semaphore: None,
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semaphore_requested_count: 0,
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};
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task
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}
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}
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fn create_idle_task() {
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let mut idle_task = create_task(idle_main);
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@ -71,13 +71,13 @@ fn main() -> Status {
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});
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assert_ne!(rsdp.load(Ordering::SeqCst), 0, "RSDP not found");
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let framebuffer_info = setup_display();
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let memory_map = unsafe { exit_boot_services(MemoryType::LOADER_DATA) };
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let pml4 = setup_paging(&memory_map, heap_start);
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let mut memory_map = unsafe { exit_boot_services(MemoryType::LOADER_DATA) };
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let pml4 = setup_paging(&mut memory_map, heap_start);
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map_kernel(KERNEL, pml4, kernel_start);
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let loader_struct = generate_loader_struct(&memory_map, kernel_start, heap_start, rsdp.load(Ordering::SeqCst), features.has_hypervisor(), framebuffer_info);
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info!("Jumping to kernel...");
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unsafe {
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(mem::transmute::<_, extern "C" fn(&LoaderStruct) -> !>(kernel_entry))(&loader_struct);
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(mem::transmute::<u64, extern "C" fn(&LoaderStruct) -> !>(kernel_entry))(&loader_struct);
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}
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}
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#[panic_handler]
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@ -19,7 +19,7 @@ fn get_table_entry(table: &mut PageTable, i: usize) -> &mut PageTable {
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table.entries_phys[i].set_write(1);
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table.entries_phys[i].set_present(1);
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}
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return table.entries_virt[i].as_mut().unwrap();
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table.entries_virt[i].as_mut().unwrap()
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}
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pub fn map(pml4: &mut PageTable, virt: u64, phys: u64, write: bool, exec: bool) {
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let virt_page = virt as usize / 0x1000;
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@ -35,7 +35,7 @@ pub fn map(pml4: &mut PageTable, virt: u64, phys: u64, write: bool, exec: bool)
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table.entries_phys[table_i].set_execute_disable(!exec as u64);
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table.entries_phys[table_i].set_present(1);
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}
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pub fn setup_paging(memory_map: &MemoryMapOwned, heap_start: u64) -> &mut PageTable {
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pub fn setup_paging(memory_map: &mut MemoryMapOwned, heap_start: u64) -> &mut PageTable {
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const NONE: Option<Box<PageTable>> = None;
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let pml4 = Box::leak(Box::new(PageTable {
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entries_phys: [PageEntry(0); 512],
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@ -70,7 +70,7 @@ pub fn setup_paging(memory_map: &MemoryMapOwned, heap_start: u64) -> &mut PageTa
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// Write Protect
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asm!("mov rax, cr0; bts rax, 16; mov cr0, rax", out("rax") _);
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// No-Execute Enable
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asm!("rdmsr; bts rax, 11; wrmsr", in("rcx") 0xc0000080 as u64, out("rax") _, out("rdx") _);
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asm!("rdmsr; bts rax, 11; wrmsr", in("rcx") 0xc0000080_u64, out("rax") _, out("rdx") _);
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}
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pml4
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}
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